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MC74VHC573 Octal D-Type Latch with 3-State Output
The MC74VHC573 is an advanced high speed CMOS octal latch with 3-state output fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. This 8-bit D-type latch is controlled by a latch enable input and an output enable input. When the output enable input is high, the eight outputs are in a high impedance state. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The inputs tolerate voltages up to 7V, allowing the interface of 5V systems to 3V systems.
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20
20 1
SOIC-20 WIDE DW SUFFIX CASE 751D 1 TSSOP-20 DT SUFFIX CASE 948E 20
VHC573 AWLYYWW 20 VHC 573 ALYW 1 VHC573 AWLYYWW
* * * * * * * * * * * w
High Speed: tPD = 4.5ns (Typ) at VCC = 5V Low Power Dissipation: ICC = 4A (Max) at TA = 25C High Noise Immunity: VNIH = VNIL = 28% VCC Power Down Protection Provided on Inputs Balanced Propagation Delays Designed for 2V to 5.5V Operating Range Low Noise: VOLP = 1.2V (Max) Pin and Function Compatible with Other Standard Logic Families Latchup Performance Exceeds 300mA ESD Performance: HBM > 2000V; Machine Model > 200V Chip Complexity: 218 FETs or 54.5 Equivalent Gates
These devices are available in Pb-free package(s). Specifications herein apply to both standard and Pb-free devices. Please see our website at www.onsemi.com for specific Pb-free orderable part numbers, or contact your local ON Semiconductor sales office or representative.
20 1
20 1
SOIC EIAJ M SUFFIX CASE 967 A WL YY WW
1 = Assembly Location = Wafer Lot = Year = Work Week
PIN ASSIGNMENT
OE D0 D1 D2 D3 D4 D5 D6 D7 GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 LE
ORDERING INFORMATION
Device MC74VHC573DW MC74VHC573DWR2 MC74VHC573DT MC74VHC573DTR2 MC74VHC573M MC74VHC573MEL
(c) Semiconductor Components Industries, LLC, 2006
Package SOIC-WIDE SOIC-WIDE TSSOP-20 TSSOP-20 SOIC EIAJ SOIC EIAJ
Shipping 38 / Rail 1000 / Reel 75 / Rail 2500 / Reel 40 / Rail 2000 / Reel
March, 2006 - Rev. 5
1
Publication Order Number: MC74VHC573/D
MC74VHC573
LOGIC DIAGRAM
D0 D1 D2 DATA INPUTS D3 D4 D5 D6 D7 LE OE 2 3 4 5 6 7 8 9 11 1 19 18 17 16 15 14 13 12 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 NONINVERTING OUTPUTS
FUNCTION TABLE
INPUTS OE L L L H LE H H L X D H L X X OUTPUT Q H L No Change Z
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MC74VHC573
I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I I I II I I I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II II I I I I I I III I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII I II I I II I II II I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I II I I I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIII I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII I III I I I IIIIIIIIIIIIIIIIIIIIIII II I I III I II I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII II II I IIIIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII II I I IIIIII II IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIII
II I I IIIIIIIIIIIIIIIIIIIIIII II III I II I I IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII II II IIIIIIIIIIIIIIIIIIIIII II I II I I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII III II I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII II I I III IIIIIIIIIIIIIIIIIIIIIII II II I I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I I I III II IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII II IIIII I I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIIIII IIIIIII I IIII IIIIIIIIIIIIIIIIIIIIIII
MAXIMUM RATINGS*
VCC Vin IIK Vout IOK Iout PD ICC SymbolIIIIIIIIIIIIII Parameter DC Supply Voltage DC Input Voltage Value Unit - 0.5 to + 7.0III V - 0.5 to + 7.0III V V DC Output Voltage - 0.5 to VCC + 0.5 - 20 20 25 75 500 450 Input Diode Current mA mA mA mA Output Diode Current DC Output Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Storage Temperature SOIC Packages TSSOP Package mW _C Tstg - 65 to + 150 * Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is not implied. Derating -- SOIC Packages: - 7 mW/_C from 65_ to 125_C TSSOP Package: - 6.1 mW/_C from 65_ to 125_C
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND v (Vin or Vout) v VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V CC ). Unused outputs must be left open.
RECOMMENDED OPERATING CONDITIONS
Symbol VCC Vin TA Vout tr, tf Parameter Min 2.0 0 0 Max 5.5 5.5 Unit V V V DC Supply Voltage DC Input Voltage
DC Output Voltage
VCC 100 20
Operating Temperature
- 40 0 0
+ 85
_C
Input Rise and Fall Time
VCC = 3.3V VCC = 5.0V
ns/V
DC ELECTRICAL CHARACTERISTICS
Symbol VIH Parameter
Test Conditions
VCC V
TA = 25C Typ
TA = - 40 to 85C Min Max
Min
Max
Unit V
Minimum High-Level Input Voltage
2.0 3.0 to 5.5 2.0 3.0 to 5.5 2.0 3.0 4.5 3.0 4.5 2.0 3.0 4.5 3.0 4.5
1.50 VCC x 0.7
1.50 VCC x 0.7
VIL
Maximum Low-Level Input Voltage Minimum High-Level Output Voltage
0.50 VCC x 0.3
0.50 VCC x 0.3
V
VOH
Vin = VIH or VIL IOH = - 50A
1.9 2.9 4.4
2.0 3.0 4.5
1.9 2.9 4.4
V
Vin = VIH or VIL IOH = - 4mA IOH = - 8mA Vin = VIH or VIL IOL = 50A
2.58 3.94
2.48 3.80
VOL
Maximum Low-Level Output Voltage
0.0 0.0 0.0
0.1 0.1 0.1
0.1 0.1 0.1
V
Vin = VIH or VIL IOL = 4mA IOL = 8mA Vin = 5.5 V or GND
0.36 0.36
0.44 0.44
Iin
Maximum Input Leakage Current
0 to 5.5
0.1
1.0
A
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29 CPD Power Dissipation Capacitance (Note 2) pF 1. Parameter guaranteed by design. tOSLH = |tPLHm - tPLHn|, tOSHL = |tPHLm - tPHLn|. 2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC / 8 (per latch). CPD is used to determine the no-load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC.
I I I IIIIIIIIIIIIIIIIIIIIIII I II II I IIIIIIIIIII II IIIIIIIIIIIIIIIIIIIIIII I II II I IIIIIIIIII II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I I I II I I I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I II I I I I II I I I I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I I I I II II I II II I I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I I II II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII II II I I II I IIIIIIIIII II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II II I I I I I I II I I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II IIIIII I I II II I I I IIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I IIIIIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIII II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I I II II I II II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I I I IIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I II I II II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I III I I I II I I I I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I II I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIII I IIIIIIIIIIIIIIIIII IIIIIIII IIIIII IIIIIIIIIIIIIII I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIII IIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIII I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIII
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns) DC ELECTRICAL CHARACTERISTICS
Symbol Symbol tOSLH, tOSHL tPLH, tPHL tPLH, tPHL tPLZ, tPHZ tPZL, tPZH Cout ICC IOZ Cin Maximum Three-State Leakage Current Maximum Three-State Output Capacitance (Output in High-Impedance State) Maximum Input Capacitance Output to Output Skew Output Disable Time, OE to Q Output Enable Time, OE to Q Maximum Propagation Delay, D to Q Maximum Propagation Delay, LE to Q Maximum Quiescent Supply Current Parameter Parameter Vin = VCC or GND Vin = VIL or VIH Vout = VCC or GND Test Conditions VCC = 5.5 0.5V (Note 1) VCC = 3.3 0.3V (Note 1) VCC = 5.0 0.5V RL = 1k VCC = 3.3 0.3V RL = 1k VCC = 5.0 0.5V RL = 1k VCC = 3.3 0.3V RL = 1k VCC = 5.0 0.5V VCC = 3.3 0.3V VCC = 5.0 0.5V VCC = 3.3 0.3V Test Conditions
NOISE CHARACTERISTICS (Input tr = tf = 3.0ns, CL = 50 pF, VCC = 5.0V)
Symbol
VOLP
VOLV
VIHD
VILD
Maximum Low Level Dynamic Input Voltage
Minimum High Level Dynamic Input Voltage
Quiet Output Minimum Dynamic VOL
Quiet Output Maximum Dynamic VOL
Parameter
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MC74VHC573
VCC V
5.5
5.5
CL = 50pF
CL = 50pF
CL = 50pF
CL = 50pF
CL = 15pF CL = 50pF
CL = 15pF CL = 50pF
CL = 15pF CL = 50pF
CL = 15pF CL = 50pF
CL = 15pF CL = 50pF
CL = 15pF CL = 50pF
4 Min Min TA = 25C Typ TA = 25C 7.6 10.1 10.7 Typ 6.7 5.2 6.7 7.3 9.8 4.5 6.0 7.0 9.5 5.0 6.5 6 4 Typical @ 25C, VCC = 5.0V 0.25 Max 4.0 14.5 11.5 15.0 11.0 14.5 11.9 15.4 Max 1.0 1.5 9.7 7.7 9.7 6.8 8.8 7.7 9.7 10 - 0.9 Typ 0.9 TA = - 40 to 85C TA = 25C Min TA = - 40 to 85C Min 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 - 1.2 Max 1.5 3.5 1.2 2.5 Max 40.0 16.5 13.5 17.0 13.0 16.5 14.0 17.5 Max 8.0 10.0 11.0 9.0 11.0 9.0 11.0 1.0 1.5 10 Unit Unit Unit V V V V A A pF pF ns ns ns ns ns ns
MC74VHC573
TIMING REQUIREMENTS (Input tr = tf = 3.0ns)
TA = 25C Symbol tw(h) tsu th Parameter Minimum Pulse Width, LE Minimum Setup Time, D to LE Minimum Hold Time, D to LE Test Conditions VCC = 3.3 0.3V VCC = 5.0 0.5V VCC = 3.3 0.3V VCC = 5.0 0.5V VCC = 3.3 0.3V VCC = 5.0 0.5V Typ Limit 5.0 5.0 3.5 3.5 1.5 1.5 TA = - 40 to 85C Limit 5.0 5.0 3.5 3.5 1.5 1.5 Unit ns ns ns
SWITCHING WAVEFORMS
tw LE 50% tPLH Q 50% VCC tPHL
D tPLH Q
50% tPHL 50% VCC
VCC GND
VCC GND
Figure 1.
Figure 2.
OE
50% tPZL Q 50% VCC tPZH Q 50% VCC tPHZ tPLZ
VCC GND HIGH IMPEDANCE VOL +0.3V VOL -0.3V HIGH IMPEDANCE LE D 50% tsu th 50% VALID
VCC GND VCC GND
Figure 3.
Figure 4.
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MC74VHC573
TEST CIRCUITS
TEST POINT OUTPUT DEVICE UNDER TEST C L* DEVICE UNDER TEST TEST POINT OUTPUT 1 k CONNECT TO VCC WHEN TESTING tPLZ AND tPZL. CONNECT TO GND WHEN TESTING tPHZ AND tPZH.
C L*
*Includes all probe and jig capacitance
*Includes all probe and jig capacitance
Figure 5.
Figure 6.
EXPANDED LOGIC DIAGRAM
D0 D1 D2 D3 D4 D5 D6 D7 2 3 4 5 6 7 8 9 D Q LE D Q LE D Q LE D Q LE D Q LE D Q LE D Q LE D Q LE LE OE 11 1 19 18 17 16 15 14 13 12 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
INPUT
Figure 7. Input Equivalent Circuit
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MC74VHC573
PACKAGE DIMENSIONS DW SUFFIX SOIC CASE 751D-05 ISSUE F
D
A
11 X 45 _
q
NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A A1 B C D E e H h L q MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_
H
M
B
M
20
10X
0.25
E
1 10
20X
B 0.25
M
B TA
S
B
S
A e
SEATING PLANE
h
18X
A1
T
C
DT SUFFIX TSSOP CASE 948E-02 ISSUE A
20X
K REF
M
L
0.15 (0.006) T U
S
0.10 (0.004)
TU
S
V
S
2X
L/2
20
11
L
PIN 1 IDENT 1 10
B -U-
J J1
N 0.15 (0.006) T U
S
A -V- N F
C D 0.100 (0.004) -T- SEATING
PLANE
G
H
DETAIL E
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IIII IIII IIII
SECTION N-N M DETAIL E
K K1
0.25 (0.010)
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 6.40 6.60 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.252 0.260 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
-W-
MC74VHC573
PACKAGE DIMENSIONS M SUFFIX SOIC EIAJ CASE 967-01 ISSUE O
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). DIM A A1 b c D E e HE L LE M Q1 Z MILLIMETERS MIN MAX --- 2.05 0.05 0.20 0.35 0.50 0.18 0.27 12.35 12.80 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --- 0.81 INCHES MIN MAX --- 0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.486 0.504 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 0_ 10 _ 0.028 0.035 --- 0.032
20
11
LE Q1 M_ L DETAIL P
E HE
1
10
Z D e A VIEW P
c
b 0.13 (0.005)
M
A1 0.10 (0.004)
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MC74VHC573/D

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